Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks

摘要

While Deep Neural Networks (DNNs) push the state-of-the-art in many machinelearning applications, they often require millions of expensive floating-pointoperations for each input classification. This computation overhead limits theapplicability of DNNs to low-power, embedded platforms and incurs high cost indata centers. This motivates recent interests in designing low-power,low-latency DNNs based on fixed-point, ternary, or even binary data precision.While recent works in this area offer promising results, they often lead tolarge accuracy drops when compared to the floating-point networks. We propose anovel approach to map floating-point based DNNs to 8-bit dynamic fixed-pointnetworks with integer power-of-two weights with no change in networkarchitecture. Our dynamic fixed-point DNNs allow different radix points betweenlayers. During inference, power-of-two weights allow multiplications to bereplaced with arithmetic shifts, while the 8-bit fixed-point representationsimplifies both the buffer and adder design. In addition, we propose a hardwareaccelerator design to achieve low-power, low-latency inference withinsignificant degradation in accuracy. Using our custom accelerator design withthe CIFAR-10 and ImageNet datasets, we show that our method achievessignificant power and energy savings while increasing the classificationaccuracy.